1. FIELD OF THE INVENTION
This invention is directed to providing a readily manufacturable thyristor with gate current turn off capability.
2. BACKGROUND ART
A power thyristor is a switching device that is used to control the switching of large currents with a relatively small control current. A common application of a thyristor is to provide variable power to a device, for example a heater or a light bulb, connected to a constant line source. The amount of power delivered to the device during each cycle is determined by the time in the cycle that a current pulse is applied to the turn-on gate of the thyristor. A conventional prior art thyristor in FIG. 1. The device comprises an n+-type cathode 101, a p-type gate 102, an n-type substrate 103, a p+-type emitter 104, and contact means connected to regions 101, 102 and 104. The device is similar to a p-n-p-n diode, except that a gate is attached to one of the base regions.
When a positive bias is applied to the anode 104 and the cathode 101 that is smaller than the value required to initiate current flow through the thyristor, the thyristor is said to be in a forward blocking mode of operation. The voltage required to initiate current flow through a thyristor is called the forward-breakover voltage. The forward-breakover voltage decreases with increasing positive current to the gate 102. When a thyristor bias exceeds the forward-breakover voltage the thyristor goes into a low impedance, high current capacity, forward-conducting, on-state. A conventional thyristor latches in the forward conducting on-state, such that load current, between the anode 104 and the cathode 101, continues to flow even in the absence of gate current. To turn a conventional thyristor off, the load current must be reduced below a threshold value, called the holding current value. This is an undesirable feature for many thyristor applications because the switching time is relatively long and additional control circuitry is required. For a more detailed description of the operation of conventional thyristors see U.S. Pat. No. 4,935,798.
To turn off a conventional thyristor using gate current requires all of the anode-cathode current, henceforth referred to as load current, to be drawn out through the gate. This requires the use of a large gate thickness to handle the high currents. However, a large gate thickness eliminates current gain, as shown by the relationship .beta..sub.0 =(2L.sub.p.sup.2)/(W.sup.2) where .beta..sub.0 is the common emitter current gain, L.sub.p is the diffusion length of holes, and W is the width of the gate. This limitation among others has prevented many prior art thyristors from having the capability of turning off the load current using gate current.
Prior art designs have been limited by the effects of high current densities that form around the contact areas when the device is turned on. Small regions of the gate near the contacts begin conducting before the rest of the gate; hence, high current densities develop in these regions. This transient rapid increase in current density is known as the "di/dt" effect. The large localized instantaneous power dissipation that results from the high current density in the regions that first begin conducting may cause irreversible damage to the device.
A common cause of di/dt failures in prior art devices is inadequate gate current. When a small gate current is used to drive a thyristor, such that it is sufficient to barely turn the gate on, the entire gate does not start conducting immediately. Instead load current is localized in small conducting regions in the gate and undesirable high current densities result. Prior art designs have used a two stage turn on process to reduce these destructive localized high current densities. The first stage is turned on with a small gate current, and this first stage then drives the main gate of the thyristor with a substantially larger current. For example, the first stage may be turned on with only a 100 mA current. This first stage may then generate a several ampere current to drive the main thyristor gate and provide adequate current to turn on the whole gate. This regenerative gate structure has limited effectiveness and substantially increases the complexity of the device.
Another technique that has been used to minimize di/dt effects in prior art designs is to slow down the turn on process. This approach also has limited effectiveness, and has the substantial drawback of reducing the speed of the device which limits the applications in which the device can be used. An additional technique that is used to reduce di/dt effects is to increase the emitter area, however, this approach is also not sufficiently effective to eliminate the problem of di/dt failures.
The di/dt effect is illustrated in FIGS. 5A and 5B. In FIG. 5A, a graph of current versus time is illustrated for a prior art design. The current begins at a relatively low value and then slowly spreads over time. FIG. 5B illustrates current density versus time for the same device. After the current turns on, the current density can be several orders of magnitude greater than the steady state level. The change in current is occurring at a greater rate than the area change (i.e. the area available for transmitting current).
To minimize di/dt effects prior art designs have used a variety of techniques including increasing the surface area of the contacts and slowing down the turn on process of the device. These techniques have limited effectiveness.
There have been a variety of developments in the field of thyristors including the following:
U.S. Pat. No. 3,465,216, issued to Teszner, describes a semiconductor switching device having at least four layers of alternate P and N conductivity types with a rectifying P/N grid in one of the intermediate layers, and at least four terminals. The terminals are connected to the anode, cathode, the grid, and at least one other intermediate layer. The device is rendered conductive by the application of a pulse between the control electrode connected to the intermediate layer and the terminal connected to the nearest outside layer. The device is rendered non-conductive by the application of a pulse between the intermediate layer and grid.
U.S. Pat. No. 3,874,956, issued to Gamo et al., describes a method of making a semiconductor switching device comprising of a PNPN or NPNP structure having four semiconductor regions, one region of higher specific resistivity of two central regions of the four regions being sandwiched between a centrally positioned junction and one of the end junctions of three PN junctions formed between the four regions. The central region of higher specific resistivity involves impurities for controlling the lifetime of carriers, and its concentration distribution being such that the impurity concentration of that portion adjacent to the central junction is higher than that of the portion adjacent to the above mentioned end junction.
U.S. Pat. No. 4,032,961, issued to Baliga et al., discloses a geometrical design criteria for a Gate Modulated Bipolar Transistor, or GAMBIT, which is a three terminal variable negative resistance device. The GAMBIT is a planar, interdigited, integrated device whose electrical characteristics show a voltage controlled negative resistance between two of its terminals. The magnitude of the negative resistance is controlled by the variation of the applied bias to the third terminal.
U.S. Pat. No. 4,037,245, issued to Ferro, is directed to an electric field controlled semiconductor diode comprising a semiconductor substrate with a uniform anode injecting region formed in one major surface of the substrate and a current controlling surface grid formed in the other major surface. The interstices of the grid include a cathode region of high injection efficiency. Means for controlling the flow of electrical current between the anode and the cathode regions is also described.
U.S. Pat. No. 4,060,821, issued to Houston et al., describes a grid structure for a field controlled thyristor. The grid structure controls the current and is interdigited with a cathode structure in which the surface area of the cathode structure is substantially greater than that of the grid structure. High forward blocking voltage gain (anode voltage/grid voltage) and low on-state losses in a turn-off type field controlled thyristor are accomplished by providing a surface grid portion and a buried portion which is connected to the surface grid structure and substantially underlies the cathode structure. The buried grid structure is constructed in a manner to provide a high aspect ratio for the channel region. A p-type anode region is described in addition to a current controlling grid structure. The grid structure consists of individual surface adjacent p+-type regions contacting buried grid elements of p-type conductivity.
U.S. Pat. No. 4,514,747, issued to Miyata et al., is directed to a field controlled SCR. The thyristor comprises a first semiconductor region of n+-type, a second semiconductor region of n-type, third semiconductor regions of p-type, a fourth semiconductor region of n--type and a fifth semiconductor region of p+-type. These regions are formed on a semiconductor substrate having two main surfaces. The U.S. Pat. No. 4,514,747 embodiment has an n-type region in the center of the p-type gate to enable gate current to be used to turn off the load current. The impurity concentration in a region intervening between a heavily doped cathode region and a buried gate region decreases from the cathode to the gate region.
U.S. Pat. Nos. 4,872,044, and 4,935,798, both issued to Nishizawa et al., are divisions of U.S. Pat. No. 4,772,926, also issued to Nishizawa et al. These three patents, U.S. Pat. Nos. 4,872,044, 4,935,798, and 4,772,926, describe a field controlled thyristor with a low impurity concentration channel region having opposed first and second major surfaces, a first main electrode region having one conductivity type and a second main electrode region having another conductivity type opposite to the one conductivity type and provided on the first and second major surfaces, respectively, and a gate region provided in the vicinity of the first main electrode region There intervenes between the channel region and the second main electrode region a thin layer region having the same conductivity type as that of the first main electrode region. The provision of this thin layer region contributes to allowing a low impurity concentration as well as a decreased thickness of the channel region for a given maximum forward blocking voltage. A trapezoidal p+-type gate structure is also described.
U.S. Pat. No. 4,837,608, issued to Nishizawa et al., is directed to a double gate static induction thyristor comprising an n--type semiconductor substrate having first and second principal surfaces opposite to each other. A first gate electrode is formed on the first principal surface of the substrate, and a second gate electrode is formed on the second principal surface of the substrate.
U.S. Pat. No. 4,841,350, issued to Nishizawa, describes a static induction photothyristor having a non-homogeneously doped gate. The photothyristor comprises a cathode, a gate, an anode, and bar components in the gate area with impurity densities which are unequal to each other.
U.S. Pat. No. 4,851,889, Matsuzaki, describes a conductivity modulated type field effect transistor, having a drain region of first conductivity type with an associated drain electrode, a conductivity modulating region of a second conductivity type opposed to that of the drain region, a channel region of the first conductivity type and a source region of the second conductivity type formed consecutively on top of one another. A gate is formed over the gate insulating film and a source electrode is formed over the channel forming region.
U.S. Pat. No. 4,984,049, issued to Nishizawa et al., describes static induction thyristor. A "buried gate" region is described including extended members disposed in a region of opposite conductivity type. Connections are made to a cathode region and an anode region that are formed on opposing surfaces of the structure. The gain of the thyristor of U.S. Pat. No. 4,984,049 is limited by a ratio of gate-anode length and the gate separation.
U.S. Pat. No. 4,985,738, issued to Nishizawa et al., describes a static induction thyristor having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control.
Previous designs, including U.S. Pat. No. 4,514,747 issued to Miyata et al., have used diffusion processes as well as epitaxial growth processes to create buried gate structures that incorporate diffusion wells or grid structures. These processes have demanding process requirements which limit their manufacturability. One such requirement is that the region around the gate well must be compensated to balance the dopant density of the well. When the dopant density of the region surrounding the diffusion well is too low, the well spreads out beyond the desired limits of the vertical channel. When the dopant density of the region surrounding the diffusion well is too high then the channel is too narrow and it may not penetrate the full depth of the gate region. A further requirement is that dopant concentration in the diffusion well must be tightly controlled because too high of a dopant concentration in the diffusion well degrades the depletability of the region, and too low of a dopant concentration impairs the turn-off capability of the device. The manufacturability limitations of the prior art devices have substantially limited their usage.